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The MiMagic 5 Applications Processor provides: 

High System Performance 220 MHz 32-bit ARM V4T Compliant RISC processor (ARM922T) with two independent 32-bit, DMA-backed, bus architecture providing separate interfaces for simultaneous access to system memory and program store eliminating shared bandwidth bottleneck. Split bus enables XIP feature optimizing system performance. Prioritized vectored interrupt reduces latency. Dynamically assignable DMA controller

Very Low System Power Consumption Low power 0.18 m 1.8 V process. SDRAM, Static Memory and LCD interfaces operate independently at 1.8 V or 3.3 V. 160 KB of internal buffer for display refresh without external memory access. Frequently used codes (e.g. MP3 Software decode) or data (e.g. MPEG-4 decoded intermediate data) can be stored in the SRAM buffer to minimize external memory fetches during program executions. Multiple power down modes including, run mode at programmable frequencies, idle and standby; partial LCD display support for mobile phone standby. Meets low power requirements of Smartphones and Pocket PCs. For Standby Mode, both CPU and system bus clocks are shut off with LCD display either on or off

Multimedia Enhancement Hardware-assist for MPEG4/H.263 video streaming and decoding. Supports CCIR 601-5. Digital camera interface, Hardware Color Space Conversion, Video Scaling, Video Overlay and Color keying. Video processing at significantly reduced CPU speed and less bus bandwidth loading saving power consumption

High throughput, Flexible, Parallel Inter-Processor Communications 16-bit Shared MailBox Interface and serial interfaces (Multiple UARTs and SPIs). A DMA-backed baseband processor can work as bus master and access the internal 160 KB SRAM buffer as a shared mailbox with minimum CPU intervention and minimum latency

Wireless connectivity Support for Bluetooth, IrDA and baseband through serial (UARTs, USB, SPI) interfaces. A parallel (shared mailbox) interface is also available for baseband processor

Low System Cost through Integration Supports low-cost NAND Flash. Rich set of peripherals including SD Card, SDIO, MultiMediaCard, USB Host and Function (including USB transceivers), serial I/O, and audio I/O, resulting in very small footprint

Multiple Boot Options Linear Flash, NAND Flash, UARTs, SD card, MultiMediaCard, Serial EPROM and unique capability to boot by another processor using Shared MailBox Interface. Useful in code development, production or for field software upgrades

The MiMagic 5 Applications Processor is ideal for mobile multimedia-enhanced personal communication, productivity, and entertainment products such as:

Multimedia Messaging Service (MMS) enabled Smartphones and Mediaphones
PDAs and Wireless PDAs
Audio/Video Players
Handheld Information Appliances

Download files:

 - MiMagic 5 Product Brief 
 

 

High Performance, ARM 922T CPU 
 32-bit RISC ARM V4T instruction set with 16 bit extensions (THUMB)
 
8 KB Instruction and 8 KB Data caches
 
Up to 220 MHz

Dual Memory Subsystem
 
Dynamic Memory Control 
Supports 16/32-bit 1.8 V/2.5 V low-power SDRAM and 3.3 V SDRAM
Two banks of up to 128 MB each, 256 MB maximum
100 MHz bus, partial refresh / self refresh support 
Static Memory Interface Control (SMI)
16/32-bit data path for SRAM, Async Flash, Sync Flash, ROM and External I/O
1.8 or 3.3 V I/O 
8/16-bit data NAND Flash 
16/32-bit Linear Flash
Five memory segments of up to 64 MB each
PC Card /CompactFlash
Interface to PC Card/CompactFlash through NeoMagic NMC1121


External Processor Connectivity
External DSP Interface
16-bit Shared MailBox Interface. 

160 KB On Chip SRAM with DMA Support
Local LCD frame buffer, up to 240X320X16bpp, reduces power and memory bandwidth requirements
Local data storage speeds up program execution
Used as Shared Mailbox by another processor
 
Display Subsystem
 
Color LCD Controller 
 - Up to 800x600 for color/mono STN/DSTN    with 2, 4, 8, and 12 bpp
 - TFT support up to 16 bpp 
 - Partial LCD display for power saving
 - Supports 1.8 V I/OCompatible with  independently


Video Subsystem 

Video Capture: CCIR 601-5 Video input port
Hardware Color Space Conversion
Video Overlay and Color Keying
Fixed Video Scaling (¹3 X, ¹2 X, 1X, 2X) 

Audio Interface with DMA

AC97 Interface (V 2.1) 
 - Stereo Audio support
 - Variable Sample Rate, 16-Bit
 - Modem support
I²S Serial Interface
 - Stereo Audio support, 16-Bit


MIIC Interface

SD Card/SDIO/MultimediaCard

Two SD (Secure Digital) 4-bit interfaces for SD Cards and SDIO devices at 24 MHz
Supports multiple MultimediaCards

USB Host (USB 1.1)
Two ports 
Host interface at 1.5 and 12 Mbps

USB Function (USB 1.1)
Full speed, 12 Mbps
Control in/out, Bulk in/out, Interrupt in, and 
Isochronous in/out transfer modes
Six end points: One CONTROL end point, two IN end points, two OUT end points, and one INTERRUPT end point 

Two USB Transceivers 
On-chip USB transceivers multiplexed with USB 
 - Host or USB function

Serial Communication Subsystem
 4 DMA backed UARTs up to 920 Kbps
 - Hardware flow control options
IrDA 115 Kbps (SIR) on UART2 and 4 Mbps (FIR) 


2 Synchronous Serial Interfaces with DMA
One SPI/Microwire interface with Master/Slave mode 
One SPI/Microwire interface with Master mode


Power Management  
Run / Idle / Standby modes
Software controlled state transitions
Gated clocks
Supports low power SDRAM (1.8 V Core/IO)
Built-in 160 KB low power SRAM for LCD frame 
buffer to reduce power consumption 
Partial LCD display support
Dynamic Frequency Switching
Reduced voltage for LCD, GPIOs, SMI, and peripherals

System Control 
Three 16 bit timers/counters, 32-bit RTC
Interrupts: 3 IRQ, 1 FIQ, multiple levels and priorities
Prioritized vector encoding reduces latency
Programmable LED output
Maximize GPIOs by turning unused peripheral pins to GPIOs
12 Channels of DMA with Memory-to-Memory DMA from/to SDRAM/SMI/internal SRAM

On-Chip Debug and ICE Support
• JTAG for MultiICE interface

2 KB On-chip Boot ROM 
Internal Boot ROM – boot through SD/
MultiMediaCard, Serial port, serial EPROM, NAND/NOR Flash, and boot by another processor using Shared Mailbox Interface


Small Footprint Package 
336-pin BGA 

Operating Range 
Core: 1.8 V± 5%
SDRAM, GPIO, LCD, SMI I/O operate down to 1.8 V
Peripherals operate down to 2.8 V
Dynamic frequency switching, software programmable from 18 MHz to 220 MHz 
Commercial/Industrial Temperature support

Estimated Typical Power Consumption

Run : 200 mW typical at 220 MHz, 1.8V
Idle : 25 mW 
Standby : 0.5 mW (LCD controller off)
    9 mW (Full Screen LCD controller on)












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